module segshow(
	input clk,
	input nRST,
	input [7:0]number0,
	input [7:0]number1,
	input [7:0]number2,
	input [7:0]number3,
	input [7:0]number4,
	input [7:0]number5,
	input [7:0]number6,
	input [5:0]on,
	output [7:0]dig,
	output [5:0]sel_on
);


parameter T5MS = 15'd50_000;

reg [14:0] time_cnt;			
reg [5:0] sel;
reg [7:0] rdig;
reg [5:0] rsel_on;
reg flag;
wire timer;

assign dig = ~rdig;
assign sel_on = ~rsel_on;
assign timer = flag;

always @ (posedge clk, negedge nRST)begin
	if(!nRST) begin
		flag <= 1'b0;
		time_cnt <= 15'h0;				
	end else if(time_cnt == T5MS)begin
		time_cnt = 15'h0;	
		flag <= ~flag;
	end else
		time_cnt = time_cnt + 1'b1; 
end


always @ (negedge timer or negedge nRST) begin
	if(!nRST)					
		sel <= 6'b000_001;				
	else if(sel == 6'b100_000)
		sel <= 6'b000_001;
	else
		sel <= sel << 1'b1;
end


always @ (*)begin
	rsel_on = sel & on;
end

always @ (*)begin
	case(rsel_on)
		6'b000_001: rdig = number0;
		6'b000_010: rdig = number1;
		6'b000_100: rdig = number2;
		6'b001_000: rdig = number3;
		6'b010_000: rdig = number4;
		6'b100_000: rdig = number5;
		default:	rdig <= 8'hff;
	endcase
end


endmodule